Highly integrated and finely patterned semiconductor integrated circuits require formation of elements in a smaller area at a higher density. Particularly, in a semiconductor memory, formation of elements in a smaller area at a higher density to produce the bit unit price at a lower price is one of important subjects.
Even in a multivalue NAND flash memory or the lowest cost memory in the art, however, difficulty in processing and limits of field effect transistors in association with the reduction in production rule make it difficult to reduce the cost more than now.
On the other hand, methods of producing memory elements at higher density may provide a memory cell having a three-dimension type structure that uses no field effect transistor. Such the memory cell may include a diode or a non-ohmic element capable of restricting current in both directions, and a memory element such as a phase change memory, a resistance variable memory, and a conductance bridge memory.
In the cell of the three-dimension type, however, the resistance of the word line or bit line increases in association with the reduction in rule and causes a voltage drop. As a result, accurate operation voltages can not be applied to all memory cells as a large problem. Therefore, the minimum cell array unit can not be made larger and consequently the chip size can be hardly reduced.
Therefore, there are needs for technologies of compensating for variations in voltage drop in memory cells (for example, Patent Document 1).    [Patent Document 1] U.S. Pat. No. 6,480,438